Programmable logic devices such as field programmable gate arrays (FPGAs) include a plurality of logic blocks. Each logic block includes one or more lookup tables the contents of which are programmable through corresponding static random access memory (SRAM) cells. For example, sixteen SRAM cells may store the contents of a four input lookup table. The configuration of an FPGA thus involves writing to numerous SRAM cells.
Configured SRAM cells in an FPGA not only control the contents of the lookup tables but also configure other components such as programmable routing multiplexers in the routing for the FPGA. The SRAM cells are typically supplied by a power supply voltage that is higher than a core logic supply of VCC for core logic. In one embodiment, the power supply voltage may equal 1.36 V whereas VCC equals 1.1 V. In this fashion, the programmable routing multiplexers may be constructed from n-channel pass gates but still pass sufficiently high binary ones due to the elevated power supply voltage driving the gates on the n-channel devices.
Although the elevated power supply voltage for the SRAM cells is advantageous for programming elements such as the routing multiplexers, the SRAM cells may then suffer from wear-out mechanisms such as hot-carrier-injection (HCI) when they are programmed (written to) at the elevated level of 1.36 V. Accordingly, there is a need in the art for more robust SRAM power regulation schemes.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.